The invention relates to the field of digital transmissions, and, more particularly, to a technique of clock alignment in a data receiver.
In a digital transmission system, information bits electrically coded with voltage or current levels to represent the basic information of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are transmitted sequentially in the form of a serial stream of bits. The receiver may receive a clock together with the data, and generate locally a replica of the transmitter clock or recover a clock from the incoming data. In all cases the receiver clock is preferably centered in the middle of the data pulse, and this condition should be maintained during operations.
According to a prior art clock recovery technique, a clock signal is extracted from a data stream using spectral information on the period of the received stream of bits. Many of these known approaches are able to align the recovered clock to the center point of the data pulses. However, these approaches may also have many drawbacks and constraints that limit their usage.
The advantages include: the receiver generates its own clock without any external clock generation (no need of expensive components to distribute clocks through the system), and the alignment between data and clock may be precisely controlled.
The disadvantages include: receivers are preferably realized in simple and fast CMOS technology, conceived for digital design and thus unsuitable for the implementation of clock recovery schemes, usually realized with analog structures; high sensibility to noise, especially when implemented in digital ASIC technology; and too slow for today""s state-of-the-art applications.
To reduce the complexity of the receivers, the alternative approach is that of generating the clock independently from the data within the receiver. This is done in the form of a precise replica of the transmission clock by using stable quartz oscillators or PLLs. Most typically, the alignment of a locally generated clock with the data is performed by feedback loops. The control loop monitors continuously the actual relative positions of the clock and data edges (fronts), and controls an array of delay elements for adjusting their relative position. Since the relative time or temporal position is important, it is irrelevant to shift the phase of the data pulses with respect to a fixed clock or vice versa.
Analog circuitry, as normally employed for implementing such control loops of clock aligners (also referred to as phase aligners), may ensure the alignment of a clock with an incoming asynchronous stream of digital data, but imposes tight constraints on the environment of the chip in which the analog circuitry is embedded. It may happen that an analog circuit that behaves well in an isolated environment becomes completely erratic when working near digital circuitry that causes injection of switching noise into susceptible parts of the analog circuit. A design goal is to keep the analog circuit isolated as much as possible from the noisy digital sectors. This problem becomes even more acute when analog parts are embedded in a digital CMOS chip, because it is extremely difficult to ensure a complete isolation between the analog part and the noisy digital parts in a normal CMOS fabrication process.
A practical analog phase aligner may be more precisely illustrated by the diagram of FIG. 1. The delay line represents the means for adjusting the phase delay between data and data synch. The phase detector is a block that compares the phase differences between clock and data synch. The loop filter is typically a low pass filter that is necessarily introduced to avoid unwanted oscillation in the feedback loop. The delay line control block adjusts the delay introduced by the delay line as a function of the filtered output of the phase detector. Typically this block performs only buffering and/or amplifying functions. In the example of FIG. 1, the phase of the data is changed in relation to the phase of the clock that is kept fixed.
A delay line usually comprises one or more variable delay stages in cascade. The propagation delay that is introduced by each delay cell can be varied continuously within a certain range through an analog control signal coming from the delay line control block. Many different implementations of variable delay cells are possible, but all of them share the concept that the delay cell is essentially an analog controlled stage. The delay of propagation of which may be varied continuously by way of an analog control signal.
A phase comparator outputs a current pulse whose amplitude is proportional to the phase difference between the edges of the data and those of the clock. This pulse is fed to a low pass filter that integrates the currents going back and forth from the phase comparator and whose output is an analog voltage proportional to the net current input to the filter.
As new applications tend to satisfy the incessant demand of broader bandwidth in digital communications for faster and greater numbers of transmission links, the limitations of the analog approaches become more evident. Analog approaches are always critical and are not easily expandable as the working frequency increases. Typically, analog approaches are custom approaches and are therefore difficult to reuse. In contrast, apparatus manufacturers are looking for approaches that can be moved from one design to another with minor changes that should not imply a complete redesign.
For each data link, a phase aligner is needed. As the number of links increases the embedding of more and more analog blocks may seriously reduce the yield of an ASIC. For example, a switch matrix for data communication for 16 links requires 16 analog blocks and in next generation products the number of the links is expected to grow up to 32 or 64. Embedding so many modules or analog circuit portions, while carefully avoiding any interference between them and the digital parts, becomes very difficult.
A way to avoid analog design complexity is to realize a loop based on the use of a plurality of selectable clock phases, according to the modified block diagram of FIG. 2. According to this known approach, a system clock is split in N phases equally spaced from each other by 360 degrees/N.
According to this control loop, the role of the phase detector becomes that of discriminating whether the current clock phase leads or lags the data edge and consequently choose the next or the previous clock phase so that the phase shift between the current clock phase and the data is kept low and less than(360/N)/2. The phase detector can be designed as a fully digital block, because it merely generates a flag to indicate if the edge of the clock comes before or after the edge of the data.
In these known phase aligners, the phase shift between the data and clock signals may be compensated only by choosing among a certain number of purposely generated different clock phases. The whole aligner system may be digital to avoid the problems associated with the integration of analog circuitry, but a major burden is represented by the need to integrate the circuits for generating and distributing N-clock phases on the chip.
Other approaches to clock recovery and clock alignment are based on sampling the data stream with a high frequency sampling signal and on monitoring the resulting logic sequences to verify and eventually adjust the period of the generated clock. However these techniques, though eliminating the need for any analog circuitry, are applicable only to relatively low speed (bit rates) links. They are unsuitable for the high speeds of state-of-the-art communication links.
An all-digital clock recovery and alignment system of this kind, is described in the European Patent Application No. 97830644.7 filed on Apr. 12, 1997, assigned to the assignee of the present invention.
It is evident of the need and/or usefulness of a digital clock alignment system suitable for the highest speed of state-of-the-art communication links (at present in the vicinity of 622 Mb/sec) that does not require the generation and distribution on the chip of a relatively large number of clock phases. Such a system is also relatively simple and readily integrated based upon a design which lends itself to be readily scaleable for future technological advances and transferable from project to project.
The main object of this invention is to provide a digital clock alignment system suitable to applications where there are many high bit rate links asynchronous with respect to a received clock. For example, when transmitting data at 622 Mb/s the duration of a valid data pulse is nominally 1.6 ns and the receiver""s clock must have its rising edge centered with respect to the data. In real cases, the xe2x80x9ceyexe2x80x9d or useful temporal window for correctly sampling the data is much narrower then the nominal duration of a data pulse of 1.6 ns. The alignment system may need to be duplicated for up to 20 or more links in a single IC in which the noise is expected to be a possible factor.
Under these limit conditions, a reliable analog module could hardly be accommodated 20 times on the chip. Even a system of the prior art, employing multiple clock phases would require relatively complex circuitry with an excessive area requirement.
All these difficulties of the known techniques are overcome by the system of the present invention which is based on a clock phase aligner in the form of a classical control loop of a delay line, to an input of which an incoming data stream is fed, wherein noise sensitivity and a large area requiring analog stages are no longer present, and wherein the anti-oscillatory or stabilizing function that in known systems is performed by a low pass loop filter, is performed by a digital state machine that checks logically any oscillatory behavior of the fully digital control loop of the system of the invention.
According to the invention, the delay line comprises a cascade of digital delay cells, each individual cell being able to assume two distinct configurations producing two selectable different delays of propagation. Each cell is controlled by the tap (output) of a respective one of the latches that make up a shift register which is fed with the signals output by a control logic circuit. The control logic circuit processes the flag signals output by a phase detector that discriminates on whether a data edge leads or lags the edge of a clock signal.
The control logic, besides preventing oscillations in the control loop, most preferably also provides a priority determining algorithm for enhancing the performance of the fully digital control loop of the clock aligning system of the invention, as will be described more in detail later.
Yet another embodiment contemplates a duplication of the digital control loop and the use of an arbiter circuit for switching from one to the other for extending the range of phase shift that may be compensated in high frequency applications.